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What are the DAC and ADC architectures in SDRs for inphase and quadrature phase channels?

Do we have separate ADC and DAC for each channel or there is some clever way that they are multiplexed to reduce area.

Usually in diagrams one DAC and one ADC is shown. But then I wonder how the inphase and quadrature phase information will be separated. Would appreciate if we can get a architectural diagram with an explanation

Rodrigo de Azevedo
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Dsp guy sam
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2 Answers2

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To add here are two diagrams showing common transceiver architectures: (1) a super-heterodyne where the down-conversion is done first to an IF frequency and then to baseband and (2) a zero-IF receiver where RF is translated directly to baseband. Note in both architectures it is arbitrary (technical / technology choice) where the ADC/DAC boundary is as either approaches could be done with baseband, IF or direct RF sampling to the extent technology allows. Ultimately, at baseband we desire a complex IQ signal to support most modern modulations which require asymmetrical spectrums about the RF carrier for maximum spectral efficiency (and hence a complex baseband signal with I and Q components). We can separate into I and Q in the analog using quadrature local oscillators and then use a dual ADC/DAC, or we can use a single ADC/DAC and then separate into I and Q digitally using a quadrature NCO.

The transmit and receive architectures need not match (Can use a ZIF transmitter and Super-het receiver for example).

ZIF

Super-het

For high efficiency with a digital IF/RF approach, quadrature sampling can be implemented at a $f_s/4$ IF frequency with a single ADC datapath interleaving the I and Q channels as as follows:

Channel I: 1 0 -1 0 1 0 -1 0

Channel Q: 0 1 0 -1 0 1 0 -1

This concept is further illustrated in the figure below. Sampling at Fs/4:

quadrature sampling

A subsequent phase rotator would be required to remove carrier offsets, or the ADC clock itself can be in the carrier tracking loop.

Placing the digital IF at $F_s/4$ or $N F_s \pm F_s/4$ also has the advantage of simplifying ADC anti-alias filter design as the images will all be equidistant.

Dan Boschen
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    re: slide 17, RX side: my instinct was to shout "hey, you need these LPFs to be on the analog side of that green line", but now I'm starting to wonder whether you couldn't simply force ADC rate and LO such that the aliases "align" – Marcus Müller Apr 29 '20 at 07:08
  • Hi Dan, could you please explain this a bit more "We can emulate quadrature sampling at a fs/4 IF with a single ADC interleaving the I and Q channels as as follows:

    Channel I: 1 0 -1 0 1 0 -1 0

    Channel Q: 0 1 0 -1 0 1 0 " what do the number patterns shown at the I and Q channels denote? Are these filter coefficients to get to $Fs_4$

     – Dsp guy sam Apr 29 '20 at 07:09
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    @Dspguysam simple! In the first sampling instant, you multiply the I signal with 1 and the Q signal with 0, add them up and then give them to the ADC. In the second sampling instant, you multiply I with 0 and Q with 1, add them up, and give them to the ADC. – Marcus Müller Apr 29 '20 at 07:11
  • @Dspguysam for clarification draw the 2D plane, label your horizontal axis I and the vertical Q. Because we always do that, draw the unit circle in there. Draw the first point, I=1, Q=0, then draw the second point, I=0, Q=1, then the third point and so on. You'll notice a pattern! It's a four-samples-per-period sampled sinusoid. Also, you're multiplying with that; that's complex mixing and shifts your signal by a fourth of the sampling rate. – Marcus Müller Apr 29 '20 at 07:14
  • @Marcus, Dan mentions this in context of a $\frac{F_s}{4}$ IF receiver ,so before feeding to ADC there is only 1 analog signal, so how do we multiple I and Q with different coefficients before feeding to ADC? – Dsp guy sam Apr 29 '20 at 07:16
  • @Dspguysam the trick it it works both ways. – Marcus Müller Apr 29 '20 at 07:19
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    @MarcusMüller I agree with you and fixed the slide (I was omitting showing the anti-alias filters since I don't have the ADC/DACs in the figure but see how I presented it would be confusing). Thanks for pointing that out. – Dan Boschen Apr 29 '20 at 10:31
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some clever way that they are multiplexed to reduce area.

Usually, the whole point is that you want that there's two ADCs running at half the rate, instead of one running at twice the rate.

If you'd rather have one running at twice the rate, don't do I and Q, but do a low-IF receiver.

Usually in diagrams one DAC and one ADC is shown. But then I wonder how the inphase and quadrature phase information will be separated.

Exactly by that diagram: The received signal is mixed with a LO and its 90°-shifted version, and both are separately low-pass filtered. These are the projections onto a 2-element orthogonal function space base. They are inherently separated (as long as your receiver works perfectly).

For DAC side: exactly the same arguments, other way around.

Marcus Müller
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