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TL;DR:

Can 2 tunable digitizers, each with an instantaneous bandwidth of X MHz and a common clock source, be used to achieve an instantaneous bandwidth of close to 2*X MHz by tuning their central frequencies and merging their output I+Q streams and if so, how?

In a bit more detail:

Say we have 2 RTL-SDR dongles, each capable of tuning to a specific frequency and sampling at 1 MS/s I+Q, i.e. each dongle has 1MHz of instantaneous bandwidth.

Now, say that there's a 1.5 MHz carrier coming in from 100.0 to 101.5 MHz. It's too wide for any of the two dongles to handle, but assuming their ADCs can be synchronised (e.g. like this), I'm thinking of tuning one dongle to e.g. 99.8-100.8 MHz and the other to 100.6-101.6 MHz, so that each dongle sees its part of the carrier and that there's a bit of an overlap between the two dongles.

Can the two I+Q streams coming from the two dongles be merged into a single stream spanning 1.8 MHz of instantaneous bandwidth, as if it was sampled by a digitizer with 1.8 MHz of instantaneous bandwidth, tuned to 100.7 MHz?

A few conceptual guidelines on how to merge the two I+Q streams would be great, a link to a GNU Radio model performing the task would be amazing. ;)

Tomislav Nakic-Alfirevic
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1 Answers1

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Yes this is commonly done but can be very challenging at high sampling rates. The requirement is that the analog input bandwidth for each A/D converter can pass the highest frequency components, and then performance is dictated by how well you can keep the delay matched between the channels such that each sample occurs at half the sample time of the other channel, as well as balance the gain, offset and timing mismatch between the channels (all of which is increasingly challenging at higher sampling rates when trying to maximize the dynamic range or effective number of bits). After that the samples are interleaved to represent the wider bandwidth signal.

Here is an example commercial part, the HMCAD1511, that utilizes such time interleaving to increase the sampling rate. This device uses 4 ADC's that can each sample up to 250 MSps, but has an analog input full power bandwidth up to 650 MHz. The four channels are interleaved to provide sampling rates up to 1 GSps.

Dan Boschen
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  • @Tomislav Did this answer your question? Please let me know if something still confuses you or select if this was satisfactory so we can close this out. Thanks! – Dan Boschen Apr 19 '22 at 12:44
  • Hi Dan, thanks for the answer. I think we're talking about different approaches. You seem to be describing using 2 ADCs in a way that each ADC samples at a different time. Produced samples can then be interleaved trivially and treated as if they come from one single fast ADC.

    What I'm interested in is using 2 ADCs which sample at the same time, but each of the inputs looking at its own section of the spectrum. What I'm looking for is a way to merge the two streams to produce a sample stream like one which would have been produced by a single ADC that's twice as fast.

     – Tomislav Nakic-Alfirevic Nov 04 '22 at 14:53
  • Ah understood- so undersampling at least for one of the ADC’s with band selection through different band anti-alias filters, right? If so I can update my answer; traveling this weekend so when I get back – Dan Boschen Nov 04 '22 at 18:47
  • The idea is that both ADCs undersample, but because they "see" different parts of the spectrum, are coherent and have a small overlap, my impression is that it should be possible to use these multiple ADCs to reconstruct the wider signal, – Tomislav Nakic-Alfirevic Nov 06 '22 at 17:21
  • Yes as long as you band select each region prior to sampling, with each filter passing a different portion of the bandwidth; does that part make sense to you? If not I will expand my answer to explain further. – Dan Boschen Nov 06 '22 at 20:58
  • That part makes sense to me. What I'm wondering is how to handle merging of the two recorded signals, i.e., filters at various stages are real filters, with roll-off. How would you go about reconstructing the original wide signal from the two undersampled streams so as to minimise distortion at the junction? – Tomislav Nakic-Alfirevic Nov 08 '22 at 14:12
  • I don't see how it would be possible to have no distortion using a single ADC since that would require a brickwall filter at the transition of contiguous bands. Consider a non-brickwall filter where we use complementary transition bands at $f_s/2$ such that the sum adds to 1 (will pass white noise contiguously). Consider a real signal just below $f_s/2$ and another just above $f_s/2$, they would both map to the same frequency in the discrete signal, so will add together but we are unable to distinguish each from the other. – Dan Boschen Nov 09 '22 at 13:39
  • Thanks for the continued attention to this matter, Dan! I'm not sure what you mean by "a single ADC", though: I'm talking about using two phase-synced digitizers, one listening to a part of the spectrum from 10 to 20 MHz and the other from 19 to 29 MHz and merging what they see into a stream like a stream that would have been produced by a single, wider digitizer that sees everything from 10 to 29 MHz at once. – Tomislav Nakic-Alfirevic Nov 09 '22 at 15:10
  • Yes sorry, I meant a single-ADC with filter for each band. The only way I see to do this is to either offset the sampling clock (which you could do more easily with the set-up you had in mind with a simple delay between the two ADC's) or with much more complication sample with two clocks phase-locked but offset in frequency. – Dan Boschen Nov 09 '22 at 17:39
  • Yes, well, the much more complicated approach that typically doesn't require hardware interventions is the one I need to learn more about. ;) – Tomislav Nakic-Alfirevic Nov 10 '22 at 15:03
  • If you're ok with using two different frequency clocks (but still phase locked to each other) then I can update my answer to detail the combining approach for the resulting samples. – Dan Boschen Nov 10 '22 at 15:51
  • Unfortunately, to my knowledge, existing hardware typically has a single master clock that is then used by both ADCs to trigger sampling. If redesigning hardware was an option, probably the simplest approach by far would be to stagger the triggers of the two ADCs so that they alternate and produce a stream that's nearly trivial to merge. – Tomislav Nakic-Alfirevic Nov 11 '22 at 15:00
  • Ok, so basically my answer as it stands. Assuming 50% duty cycle, you can invert the sampling clock to sample on the falling edge and use a matching delay buffer for the rising edge. – Dan Boschen Nov 11 '22 at 19:06
  • Your answer would stand if modifying HW was an option, but since it isn't, I'll have to keep looking for a solution. Thank you for the effort and persistence! – Tomislav Nakic-Alfirevic Nov 14 '22 at 08:16