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Does pipelining a 3 tap FIR Filter change the output of the filter?

I understand the output stays the same but how do I prove that? I am a little confused

as we add two more delay elements and am not sure how to go about this.

Rahul Seth
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  • what does "pipelining" mean to you? It's not clear what you do to what implementation of an FIR filter! (there's different forms of FIR filters, and there's many ways something like these might be "pipelined" in different contexts, on different hardware, so I'm really stumbling in the dark here) – Marcus Müller May 05 '22 at 20:42
  • Pipeline a filter to increase the throughput of the data with a tradeoff with latency. I am trying to understand the output of the filter is affected in a pipeline system vs direct form. – Rahul Seth May 05 '22 at 20:44
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    Again, it's not clear how your filter looks before and after. You're assuming there's only one way a filter could be implemented. and only one way something can be pipelined. both are wrong. – Marcus Müller May 05 '22 at 20:44
  • so, can you maybe tell us what your actual implementation of the 3-tap FIR before "pipelining" looks like? and how after? Or, even better: write down exactly what the steps are you are doing to come from the "before" to the "after"? – Marcus Müller May 05 '22 at 20:48
  • Ben's answer reads very plausibly! Gotta admit, I was not aware of the terminology here, and must apologize! – Marcus Müller May 05 '22 at 21:17
  • Just a general comment regarding pipelining: It should never change your output. It's supposed to maximise throughput at the cost of latency in hardware implementations. Pipelining just splits the hardware resources up so that they can be used concurrently while there is still old data in the pipeline, improving power efficiency, too. If it changes your results (apart from the delay caused by the additional latency), you're doing it wrong. – Jazzmaniac May 06 '22 at 13:01

1 Answers1

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The transfer function of a 3-tap FIR filter is $ H(z) = {b_1 + b_{2}z^{-1} + b_{3}z^{-2}} $

Unpipelined FIR

Now assuming you add a pipeline delay of 2

Pipelined FIR

The transfer function becomes

$$ H_{pipelined}(z) = {b_1z^{-2} + b_{2}z^{-3} + b_{3}z^{-4}} $$

$$ H_{pipelined}(z) = z^{-2}H(z) $$

There's gonna be a 2-sample delay. However if you simply "ignore" this delay, then you can say the transfer function stays the same.

The proof is pretty straightforward, each "path" from x[n] to y[n] encounters two more delay elements compared to the unpipelined implementation.

Ben
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  • ah! interesting, haven't seen "pipelined" used like that before (I would have just called this "delayed")! If that is common terminology, I might owe user62759 an apology! I'm very much looking forward to an explanation how $H_{pipelined}$ is (or implies?) a more pipelined structure than $H$ does! – Marcus Müller May 05 '22 at 21:10
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    ah, so the pipelining here is that the addition doesn't happen in the same time step as the multiplication with the taps! – Marcus Müller May 05 '22 at 21:17
  • @MarcusMüller Yeah, the goal here is to reduce the combitional delay from a delay element to another delay element. Decreasing the combitional delay makes it possible to increase the frequency. – Ben May 05 '22 at 21:30
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    Another approach that achieves the same goal is the reverse flow diagram (reverse all arrows, adders become branches and branches become adders)- can you comment on how that compares? – Dan Boschen May 06 '22 at 00:57
  • Thank you, Ben! So, If I were to compute the output for the FIR filter (not pipelined), it should be y = ax(n) + bx(n-1) + cx(n-2); this should be the same for the pipelined 3 tap filter as well? @Ben – Rahul Seth May 06 '22 at 01:34
  • @RahulSeth The output is the same, except that the first 2 outputs will be 0, after these first 2 zeros, the output of the pipelined filter will be the same as the original filter. – Ben May 06 '22 at 11:51
  • @DanBoschen I will look into it. It could be promising – Ben May 06 '22 at 12:00
  • @Ben You or someone else mentioned elsewhere that it may be less prevalent due to the structure available in the standard dsp blocks – Dan Boschen May 06 '22 at 12:14