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We are developing a high volume product using a lot of CM3s and we're looking into some power-up sequencing issues. I found the following on one of the forums from 2014 (I assume it refers to the CM1). From Powering the compute module:

So the minimum supplies are 1V8 and 3V3. You need to sequence the supplies so that 3V3 comes up at exactly the same time or before 1V8 (you can see on the CMIO schematic that the EN2 pin of the SMPS has an RC delay ensuring 1V8 comes up after 3V3).

James Adams (Raspberry Pi - COO & Hardware Lead)

Is this still an important consideration for the CM3s?

And as a side question, what cores do the two rails power? Can the CM3 run on 3v3 alone for a short time at boot; enough to sequence the other rails properly with GPIO under f/w control?

Greenonline
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Bruce Koball
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1 Answers1

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From the latest (Jan 2019) CM3+ datasheet (section 7.1) - https://www.raspberrypi.org/documentation/hardware/computemodule/datasheets/rpi_DATA_CM3plus_1p0.pdf

Supplies should be staggered so that the highest voltage comes up first, then the remaining voltages in descending order. This is to avoid forward biasing internal (on-chip) diodes between supplies, and causing latch-up. Alternatively supplies can be synchronised to come up at exactly the same time as long as at no point a lower voltage supply rail voltage exceeds a higher voltage supply rail voltage.

I'm similarly designing a volume product using the CM3(+). I'm using a 1V8 LDO from the output of a 3V3 DC/DC Buck circuit, so planning to have an RC circuit from the 3V3 to drive the 1V8 enable pin, to give a delay of 5-10ms. This is about how long it takes the 3V3 buck to rise from 1.5V (the enable threshold of the 1V8) to the full 3.3V. But I will refine at prototype stage once I can see oscilloscope plots.

kevinb456
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