Minted vhdl show ¡ instead of <

Question

I have some troubles with my latex document. I'm using minted to put on my file some VHDL code. However, when i compile it, all < are replaced by ¡. Does anyone have an idea ?

Here is an example :

\documentclass{report} 
\usepackage[utf8]{inputenc}
\usepackage[french]{babel}
\usepackage{minted}
\begin{document}
\begin{minted}[fontsize=\footnotesize, linenos, autogobble, breaklines]{VHDL}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sept_segment2 is
Port (
    switch_seg : in STD_LOGIC_VECTOR (3 downto 0);
    switch_an : in STD_LOGIC_VECTOR (3 downto 0);
    an : out STD_LOGIC_VECTOR (3 downto 0);
    seg : out STD_LOGIC_VECTOR (6 downto 0)

);
end sept_segment2;

architecture Behavioral of sept_segment2 is

begin

seg <= "1000000" when switch_seg = "0000" else
    "1111001" when switch_seg = "0001" else
    "0100100" when switch_seg = "0010" else
    "0110000" when switch_seg = "0011" else
    "0011001" when switch_seg = "0100" else
    "0010010" when switch_seg = "0101" else
    "0000010" when switch_seg = "0110" else
    "1111000" when switch_seg = "0111" else
    "0000000" when switch_seg = "1000" else
    "0010000" when switch_seg = "1001" else
    "0001000" when switch_seg = "1010" else
    "0000011" when switch_seg = "1011" else
    "1000110" when switch_seg = "1100" else
    "0100001" when switch_seg = "1101" else
    "0000110" when switch_seg = "1110" else
    "0001110";

an(0) <= not switch_an(0);
an(1) <= not switch_an(1);
an(2) <= not switch_an(2);
an(3) <= not switch_an(3);

end Behavioral;
\end{minted}
\end{document}

I have tried in several environments (and on overleaf). It always shows ¡ instead of <. Any ideas ? Thanks !